Re: More CPLD explorations

From: Gerrit Heitsch <>
Date: Wed, 26 Feb 2014 17:13:03 +0100
Message-ID: <>
On 02/25/2014 09:44 PM, wrote:
> On 2014-02-25 at 20:49:07, Gerrit Heitsch ( wrote:
>> The fun part is, if you look at a chip itself and measure just between
>> +5V and GND of that chip, everything is a bit noisy, but not really
>> bad.
>> It's just that the ends of the board in relation to each other do
>> funny
>> things. The 1V peak-to-peak is only a few ns, and a half cycle is
>> about 500ns.
> Well, this doesn’t mean such thing can be “written off” due to the length of the pulses. Of course it depends on various things but it still can be a disruptive factor for regular operations even if those are short.

Also, remember, the image I mailed you shows the difference in GND 
potential between the 2 points far away from each other. When you take a 
closer look at Vcc and GND on each IC, it's still noisy, but a lot less so.

>> After all, the board is working…
> “Barely” as gpz noted ;-) No, kidding - it really depends on “what”, “when” and “where”. Might as well be only a part of the circuit (“where”), which is not critical (“what”) and/or only at times “when” this part is not in use.

No, my KU is working just fine, no matter what I throw at it, so the 
'barely' is something I don't subscribe to.

If it'd get flakey  when hot/cold or with specific workloads (certain 
demos come to mind), I'd call it 'working barely'.


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Received on 2014-02-26 17:00:12

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