Marko Mäkelä wrote: > > On Tue, 5 Oct 1999, Nicolas Welte wrote: > > > So a 'clean' double clock is not achievable because of the refresh > > cycles. > > Not on the C128 either. It'll switch the processor to single clock for > the 5 refresh cycles. I know. But on the C128 it's even worse than this, because clock stretching occurs on only some I/O accesses. So you never really know if an I/O access at 2MHz speed takes one or two cycles. The 264 design doesn't seem to suffer from this, but then it has that weird Phi2 clock which must make it nearly uselees to use 6522/6526 timers there. No wonder the timers are in the TED. Nicolas - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail firstname.lastname@example.org.
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