Levente Hársfalvi wrote: > Seems like there should be just one way to go: take the beast to an > oscilloscope an make some diags; PHI0 against MUX, PHI0 against PHI2, > PHI0 against AEC' and so on, in both clock modes. Okay, maybe I could do this on some weekend in my lab. I have a two channel DSO with TV trigger capability here, so I can trigger onto any scanline and then analyze any two other signals simultaneously. But of course I need to know more about what to expect here. >From what I read so far the TED seems to do things quite differently from what I thought. It still has traditional bad lines (but more), which stop the CPU completely via BA/RDY and then disable the CPU bus with AEC. The clock signals are similar to the C128 after all, but the two clock modes are controlled differently. The TED automatically selects single clock mode if it needs the bus, and double clock mode is only active where the display is inactive, except where the refresh occurs. So a 'clean' double clock is not achievable because of the refresh cycles. But a clean single clock mode can be achieved by using the appropriate control bit. Is this correct so far? Nicolas - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail firstname.lastname@example.org.
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