Re: 264 series questions

From: Levente Hársfalvi (
Date: 1999-10-04 20:46:33


> According to the Plus/4 timing diagram, the CPU gets a Phi0 clock signal
> which looks very different from a standard signal with 50% duty cycle if
> in double clock mode. _Maybe_ some timing circuits in the 8501 are based
> on the average clock frequency (which is about 1MHz in single clock
> mode) and not on the length of the active cycle (which still is
> equivalent to about 2MHz, even in single clock mode). _Maybe_ some
> signals have to be tweaked with the GATE IN input because of this.

Seems like there should be just one way to go: take the beast to an
oscilloscope an make some diags; PHI0 against MUX, PHI0 against PHI2,
PHI0 against AEC' and so on, in both clock modes.

I'd also give a try to draw at least _some of these diags from the same
PAL Plus/4 but with the TED set to NTSC mode. Then the resulting
processor clock would be 17.73/16 and 17.73/8, above 1.1 and 2.2 Mhz;
these are pretty off to the nominal clocks and would give an answer if
the control line timings are based on what. If they change, they're
based on the PHI0 clock. Else, on monostables.

> BTW, how do the TED memory accesses work? I assume that since unlike the
> VIC-II it gets all information from system memory and there is no extra
> color memory, it must have more accesses to the memory than the VIC-II.

Yes. As Marko mentioned, it has simply two bad lines; one for colors,
one for character pointer data.

> It should also be true that the TED memory clock always runs at about
> 2MHz and uses, speaking in quarters of a full single clock cycle, the
> quarters Q1, Q2 and Q3 during active display, and only the quarters Q1
> and Q3 in the retrace areas. So the CPU gets only quarter Q0 in single
> clock mode and quarters Q0 and Q2 in double clock mode.

Not really. The TED unfortunately, doesn't utilize the more available
bus cycles; they decided to use two bad lines instead :-(.

If we don't count the actual weird timings of the 8501/8360 bus, in
single clock mode the Plus/4 video timings look much like the C64 video
timings (except the more bad lines, the different cycles per line,
different raster counter values and so on). The bitmask data fetch, the
pointer data fetch (this latter with transparent DMA) are performed
exactly like in the C64. ...Remember, the TED _always changes PHI0 to
single clock mode when it performs whatever action in the memory.

The oscilloscope measurements could answer the questions, which quarters
are used and actually performed by whom. But each even or each odd
quarters are idle, I'm sure.

> I also found what I think is the TED patent document on the net, but it
> doesn't speak of the interfacing to the 8501 CPU :-( They only speak
> about the 6510.

Where could these patents be found?

I received a lot of them from Frank (...they were one of the best docs
I've ever read about C=, one even helped me to solve the problems I had
with the mouse interface). (He told me he received the files from
Marko.) But of course I'd be interested in finding more.


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