On 10/22/2013 08:53 PM, Bil Herd wrote: > Very close, its actually /CAS going high if memory serves as it's the > last signal of importance in the cycle; data will be latched on a write > cycle on the rising edge of CAS providing the setup time is met. In the datasheet for a Samsung 4164 I have, it says that data to be written must be valid at or before _W or _CAS go LOW (whichever is later). So that would mean that the end of the cycle timing is not that important for DRAMs as it is for SRAMs since it samples the data to be written near the beginning. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2013-10-22 20:00:04
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