RE: The ultimate UltiMax cartridge

From: Bil Herd <>
Date: Tue, 22 Oct 2013 14:53:01 -0400
Message-ID: <>
Very close, its actually  /CAS going high if memory serves  as it's the
last signal of importance in the cycle; data will be latched on a write
cycle on the rising edge of CAS providing the setup time is met.  Unlike
the 6502 there is very little hold time requirement, as soon as /cas goes
everything can get starting changing immediately.  (And needs to to meet
/RAS setup for address)  At one time /RAS and /CAS got pulled high
together but we started to make /RAS go high sooner so we could meet the
Time Ras Precharge, Micron DRAMs were especially sensitive to RAS

I was thinking about doing a video explaining the timings of a 6502 based
system in general, then with shared bus, then with DRAM but I didn't know
if that would be redundant to what everyone already knows.


-----Original Message-----
[] On Behalf Of Gerrit Heitsch
Sent: Tuesday, October 22, 2013 2:40 PM
Subject: Re: The ultimate UltiMax cartridge

On 10/22/2013 07:54 PM, wrote:
> On 2013-10-22, at 18:36, Gerrit Heitsch wrote:
>> There is a reason why all simple 6502 systems I have seen (that
includes the 1541) gate R/_W with PHI2 when talking to a SRAM.
> I noticed it too, and that's one of the things I kept asking myself
about for some time. Would you be so kind as to elaborate on that reason?

On a normal 6502 system, the address lines are not tristate (no AEC
signal), but the data lines are which allows things like running two
6502 on the same data bus if you invert the clock for one of them and take
care of the address lines with multiplexers to allow shared RAM access.
This is how the IEEE floppy drives with 2 CPUs operate. Like the
8050/8250 for example.

(The 2 CPUs are UAB15 and UAB4)

Now, once PHI2 goes LOW, the data lines go offline while the address lines
are still active (not 100% sure about R/_W here, I think it stays active
too). This means whatever chip was selected at the time will stay
selected. Doesn't matter for a read cycle, but kind of sucks for a write

With a 6510 or the like on a shared bus, this is about the same, with the
differences that whatever the CPU shares the bus with will drive the
address lines while PHI0 is LOW. Unless that chip drives R/_W actively
(VIC does not, TED does), at the end of a write cycle, AEC will take R/_W
from the CPU offline, leaving the line to the mercy of a pullup (if
present). Does it rise fast enough to end the write cycle for the RAM
before the new addresses are valid and, a propagation delay later, _CS
takes the RAM off the bus?

It's a bit less complicated with DRAM, there _RAS going HIGH again marks
the end of the cycle, no matter what the other signals do. This is
reflected in the C64, with the exception of the 250469 board, the _WE pin
of the DRAM is directly connected to R/_W from the CPU and it works.
_WE for the Color-RAM (2114 SRAM) is routed through the PLA though.

That's my understanding of how it works... Corrections welcome.


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Received on 2013-10-22 19:03:08

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