RE: The ultimate UltiMax cartridge

From: Bil Herd <>
Date: Tue, 22 Oct 2013 11:31:11 -0400
Message-ID: <>
Most of the time I use Phi0 if available as Phi2 almost occurs too late for
many things. I also try to keep the delay to one or two gates from the clock
transition on Phi0 or one on Phi2.  Two gates is almost always a deal
breaker in the older logic if you add up maximum possible delays; though it
may be okay for smaller runs but results in higher percent scrap in larger

The 6502 will let go of the datalines very quickly and you need to have
cleaned up your write strobe by then as well as held everything absolutely
stable until the end or you can end up with a corrupted write cycle.

Even read cycles need the address lines/IOSel held absolutely still so that
the read data times are met for the 6502, 5-10ns after Phi the data still
has to be valid, if there is a "gotcha" timing in the 6502 this is it.  One
problem is that it can take a couple of 10s of nanoseconds to make data
stable coming out of memory, but it only takes a few nanoseconds on some
devices before the "wiggle" on an input propagates as an unknown
(corruption) to the output.

If the system is in a shared bus structure (C64 was, Vic20 was not) then it
gets a little trickier.

Sorry I just caught the end of the discussion so I may be answering out of
context.  I did send an email to one of the designers of max to see if he is
interested in answering any questions if there are any major ones about why
or how.

-----Original Message-----
[] On Behalf Of Gerrit Heitsch
Sent: Tuesday, October 22, 2013 11:17 AM
Subject: Re: The ultimate UltiMax cartridge

On 10/22/2013 10:47 AM, Michał Pleban wrote:
> 27C801.CS = /ROMH & /ROML
> 27C801.A13 = /ROML
> 27C801.OE = 6116.OE = ! RW
> 6116.WE = RW

As far as I know, with a 65xx-CPU, you need to incorporate PHI2 into the
R/_W signal (R/_W can only go LOW if PHI2 is HIGH), or is this already done
inside the MAX?


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Received on 2013-10-22 16:04:25

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