On 10/22/2013 06:45 PM, Michał Pleban wrote: > Hello! > > Gerrit Heitsch wrote: > >> What's the latency in the _CS signal? The delay from the PLA and all the >> gates works the other way too, meaning even though the CPU is done and >> VIC has taken over the bus with AEC, the _CS signal will still be low >> for a time. Doesn't matter with a ROM, but with a RAM that can corrupt a >> write cycle. >> There is a reason why all simple 6502 systems I have seen (that includes >> the 1541) gate R/_W with PHI2 when talking to a SRAM. > > I disassembled the MAX BASIC cartridge and the R/_W signal goes directly > to the SRAM without any gates. So hopefully this will work. Well, Good luck then. But if you run into strange problems with the RAM, keep the R/_W line as a probable cause in mind. Especially since current RAM is a lot faster. The internal RAM of the MAX doesn't use R/_W from the CPU, they use something that was run through the PLA. If the 6566 behaves like the 6567/69, then it doesn't drive the R/_W line at all. Once VIC takes the CPU off the bus with AEC, the line will slowly climb to HIGH with a pullup (1.5KOhm in the C64, no idea if installed in the MAX). Together with the propagation delay in the PLA for _CS, that _could_ cause trouble, depending on the RAM. If you want to gate R/_W, a 74LS139 can be used for the job. See the 250466 board for the C64 and the unused U11 / J3 combination. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2013-10-22 18:02:24
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