RE: The ultimate UltiMax cartridge

From: Bil Herd <>
Date: Tue, 22 Oct 2013 13:10:16 -0400
Message-ID: <>
That can work when another CE/CS pin on the RAM line creates an end-of-cycle
prior to the R/W line wandering off.  (Some hook Phi to this directly as
long as they watch the data hold read)

 In some systems the Read Write line acts as a strobe, for example with
Intel the line is a write strobe /WR and needs no other qualification as it
is mean to be edge sensitive.

In the '02 the R/W line doesnt have timing information in it in the form of
a strobe of any kind (other than it will try to go high via RC on a VIC
cycle), it is more like information that is valid at the falling edge of
Phi, much like address lines and read data. All of this information has to
be valid as a setup time before Phi goes low and must hang around for
another 5ns or so to meet Hold Times in Data Read.

Wiggling the addresses or chip selects while R/W is low can cause corruption
to multiple and unpredictable places. I have done this when missing a
covering term in a PLA; in a transition from one true state to another there
was a moment in between where the output was unknown, and it was enough to
cause occasional corruption.


-----Original Message-----
[] On Behalf Of Michal Pleban
Sent: Tuesday, October 22, 2013 12:45 PM
Subject: Re: The ultimate UltiMax cartridge


Gerrit Heitsch wrote:

> What's the latency in the _CS signal? The delay from the PLA and all
> the gates works the other way too, meaning even though the CPU is done
> and VIC has taken over the bus with AEC, the _CS signal will still be
> low for a time. Doesn't matter with a ROM, but with a RAM that can
> corrupt a write cycle.
> There is a reason why all simple 6502 systems I have seen (that
> includes the 1541) gate R/_W with PHI2 when talking to a SRAM.

I disassembled the MAX BASIC cartridge and the R/_W signal goes directly to
the SRAM without any gates. So hopefully this will work.


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Received on 2013-10-22 18:00:09

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