Re: 6510FPGA Suggestions?

From: Ingo Korb <>
Date: Tue, 27 Aug 2013 12:27:37 +0200
Message-ID: <> writes:

> built-in. That would mean Xilinx then. How about the software for it? Is
> it palatable? What do you use?

Well... all software sucks, but hardware synthesis software sucks
harder. ;) Xilinx ISE can be a bit crash-happy at times, I've seen it
die just by hitting F1 in its internal text editor once. The problem
seems to be restricted to the GUI though, if you use a design flow based
on the command line tools I haven't seen any crashes yet.

Altera Quartus appears to be a bit better regarding crashes, but it
isn't completely immune and it has annoyances in other areas. For
example I much prefer the handling of initialized inferred block RAMs on
the Xilinx side compared to Altera.

> Huh, you made me googling around this and discovering that you were
> involved in converting the
> into Verilog?!

I wasn't, Peter Monta wrote the converter. I just added a bit of wrapper
code to adapt the converted 6502 core to a few real systems.

> Wow.. I guess that should be the ultimate solution in terms of
> compatibility,

It's not, the timing is very different and there are some differences
in the undocumented opcodes as you have noticed. The timing difference
was the main problem making it run in an Apple II and C64, I had to add
a shift register to change the phase alignment of the Phi0 clock to
ensure that the Phi2 clock generated by the 6502 (and thus all signals
that relate to it) matched a real chip. That was enough to run simple
programs, but anything that heavily depends on exact timing (e.g. floppy
accesses on the Apple II or Demos on the C64) still had issues.

> that it still fails on 16 unsupported opcodes. How is that if this is
> such a low level simulation? I know there were different 6502
> implementations but shouldn't this one work exactly as the cpu variant
> it was based on?

It's a relatively low-level simulation, but it's not a real chip. At
least two of the undocumented opcodes in the C64 are affected by analog
conditions, i.e. on the same CPU they can give different results
depending on the chip temperature and power supply. Some others depend
on the state of the external address bus while the instruction executes
which may be influenced by the GODIL's voltage translators and probably
also the changed timing of the transistor-level simulation running in
the FPGA.

> Which would you recommend? Possibility to work outside of Windows not
> mandatory but very much preferred.

Back when I did the 6502-netlist experiments I had access to a Digilent
XUP USB-JTAG programming "cable", but I can't recommend them - they're
quite expensive and appear to have a rather high failure rate.


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Received on 2013-08-27 11:00:03

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