Re: FPGA/CPLD different approach

From: Ingo Korb <ml_at_akana.de>
Date: Tue, 27 Aug 2013 12:34:12 +0200
Message-ID: <uhaeb5snv.fsf@dragon.akana.de>
Bil Herd <bherd@mercury-cg.com> writes:

> I have gone through some test fitting but haven't really checked out
> GODIL, for instance can they program the VCC and Ground pins or do
> they have to physically configure?

They can be freely configured using jumpers, but as Didier noted the
pinning of those headers is a bit weird. IIRC the DIL pin alternates
between the left and right side of the header and the other pin
alternates between 5V and GND for each row, so you can select GND and 5V
for any DIL pin by setting the jumper either horizontally or
vertically.

> I suspect that to keep the cost
> down that the PCB might be wider than the .6" DIP but didnít yet
> research if thatís a show stopper.

It's much wider and longer - the board is 33.5 mm x 74.3 mm, the DIL
interface at the bottom appears to be centered. The overall height
including the DIL pins is ~20 mm.

-ik

       Message was sent through the cbm-hackers mailing list
Received on 2013-08-27 11:01:30

Archive generated by hypermail 2.2.0.