Re: 6510FPGA Suggestions?

From: Mark McDougall <msmcdoug_at_iinet.net.au>
Date: Mon, 26 Aug 2013 12:22:17 -0400
Message-ID: <58og682r9x1tf2kmenke40uw.1377534137956@email.android.com>
Apologies for my misunderstanding!



Sent from my ASUS Pad

Istvan Hegedus <hegedusis@t-online.hu> wrote:

>Mark,
>I thought I said the same as you. Maybe my English is not the best, but I 
>said exactly the same that this FPGA64 CPU uses a fully synchronous design 
>with clock enable (when I said it "slows" down there I meant the clock 
>enable signal) and that is the best approach.
>I said it is a drawback however because I want to interface this 6510 to 
>external dram chips which are slow. The CPU is however still fast because it 
>will do its job with the 1st clock cycle (fast clock) and then it suspends 
>for the rest of the clock cycles until the 1MHz time elapses. Old dram chips 
>however provide/expect the data out of the CPU's running cycle.
>If you put it inside the GODIL then you need some tricks to handle properly 
>the timings of a C64. Indeed my plan is to create a 8501 in GODIL to use in 
>plus/4.
>
>Istvan
>
>
>
>-----Original Message----- 
>From: Mark McDougall
>Sent: Monday, August 26, 2013 3:43 PM
>To: cbm-hackers@musoftware.de
>Subject: Re: 6510FPGA Suggestions?
>
>You are completely wrong. The best approach is a fully synchronous design 
>with a clock enable.
>
>
>
>Sent from my ASUS Pad
>
>Istvan Hegedus <hegedusis@t-online.hu> wrote:
>
>>Hi,
>>
>>I have been investigated these cores too and found FPG64's 6510 code the
>>closest implementation. I am currently playing experiments with it and one
>>drawback is that it uses fast clock (33Mhz) and slows the CPU down with the
>>enable signal. This however is needed in order not to violate the clock
>>domain of the whole FPGA64 design. It can be driven with slower clock speed
>>too but it is not a good concept to have different clock speeds in your
>>FPGA.
>>
>>http://www.syntiac.com/fpga64.html
>>
>>Br
>>Istvan
>>
>>
>>
>>-----Original Message----- 
>>From: silverdr@wfmh.org.pl
>>Sent: Saturday, August 24, 2013 12:41 AM
>>To: cbm-hackers@musoftware.de
>>Subject: 6510FPGA Suggestions?
>>
>>Since for some time I am walking circles around the FPGA/CPLD bandwagon, I
>>thought it might be time to have a closer look. I checked opencores and
>>tried to decide where to spend some money (Altera, Atmel, Xilinx, ...?) 
>>that
>>would be able to implement a 6502 and an I/O port together with some RAM 
>>and
>>ROM modules. My n00b questions to the more experienced fellows:
>>
>>- how many kgates can be needed for something like I mentioned above?
>>- what would be the best h/w platform/vendor and why?
>>- what is the most complete/reliable 6502 core to use as starting point?
>>- what can you suggest or warn about?
>>
>>Cordially,
>>
>>-- 
>>SD!
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>>
>>
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>
>
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Received on 2013-08-26 17:03:43

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