RE: FPGA/CPLD different approach

From: Mark McDougall <>
Date: Mon, 26 Aug 2013 12:20:52 -0400
Message-ID: <>
The trick is to use non-Altera SPI flash devices - much cheaper!

Sent from my ASUS Pad

Bil Herd <> wrote:

>Correct, the Altera line needs an external source to load from (I still call
>it the font but I am probably wrong).  I have done a design were the FPGA
>was $1 and the eeprom was $10, which just sucked.
>Altera CPLD don’t need to be loaded every power cycle.
>Altera is coming out with flash based devices next year according to the FE
>for my area.
>I usually do away with the EEPROM if there is another processor nearby, for
>example if the design is on a PCI card I make the main system program the
>FPGA via a JTAG-like port.  Also makes it easy to reprogram hardware in the
>-----Original Message-----
>[] On Behalf Of
>Sent: Monday, August 26, 2013 9:22 AM
>Subject: Re: FPGA/CPLD different approach
>On 2013-08-26, at 14:38, Michał Pleban wrote:
>>> I understand. What If I forget the CPU emulation and want to build only
>>> some RAM, ROM and one or two 8bit bi-directinal I/O ports, all available
>>> for the original CPU to interact with - what would you suggest? Can one
>>> easily make such structures (RAM, ROM, I/O port) available for 6502 from
>>> within a CPLD/FPGA and which would be "better" in such case?
>> ROM and RAM are costly in terms of re-programmable logic. If you need
>> these, you will end up using a FPGA anyway.
>Why is it so? I read somewhere in Altera docs that /ROM/ is not available in
>[their MAX series] CPLDs. Does that mean it is not available in /any/ of
>them? Sorry if that's a n00b question but I also read somewhere that FPGAs
>have to be given some external boot rom, while CPLDs don't.
>> If you need only I/O, then you can use a CPLD as well, there are still
>> 5V ones available (though more expensive than 3.3V).
>Like the "original" Altera MAX I guess?
>For what I think of doing I'd need about a dozen of chips. RAM, ROM, I/O and
>some glue as well. When I counted those, it triggered me to eventually start
>thinking of putting all of those into one chip, presumably only with some
>level adapters like on the GODIL and am now trying to learn enough to make
>somewhat educated decision...
>       Message was sent through the cbm-hackers mailing list
>       Message was sent through the cbm-hackers mailing list
Received on 2013-08-26 17:03:20

Archive generated by hypermail 2.2.0.