Re: FPGA/CPLD different approach

From: Mark McDougall <msmcdoug_at_iinet.net.au>
Date: Mon, 26 Aug 2013 12:19:44 -0400
Message-ID: <23n4qwd5qewhwqsg2eevihah.1377533984381@email.android.com>
The larger FPGA's have hundreds of kB actually. I'm using a Stratix device with full 64k ram along with ROM.



Sent from my ASUS Pad

Ed Spittles <ed.spittles@gmail.com> wrote:

>If you mean to have the ROM/RAM on-chip, as opposed to hooking some up to an external address or data bus, you can certainly do that with Xilinx, and I think with others too.  The larger FPGAs have more available, but something like 24kbytes is the most you are likely to see - no chance of a full 64k memory map.
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>Although what you have onchip is RAM, you do get to define the initial contents at powerup, which makes it more like ROM if you do that, and if you like you can disallow writes, which makes it entirely like ROM.
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>Hope this helps
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>Ed
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>On 26 August 2013 14:22, <silverdr@wfmh.org.pl> wrote:
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>On 2013-08-26, at 14:38, Michał Pleban wrote:
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>>> I understand. What If I forget the CPU emulation and want to build only some RAM, ROM and one or two 8bit bi-directinal I/O ports, all available for the original CPU to interact with - what would you suggest? Can one easily make such structures (RAM, ROM, I/O port) available for 6502 from within a CPLD/FPGA and which would be "better" in such case?
>>
>> ROM and RAM are costly in terms of re-programmable logic. If you need
>> these, you will end up using a FPGA anyway.
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>Why is it so? I read somewhere in Altera docs that /ROM/ is not available in [their MAX series] CPLDs. Does that mean it is not available in /any/ of them? Sorry if that's a n00b question but I also read somewhere that FPGAs have to be given some external boot rom, while CPLDs don't.
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>> If you need only I/O, then you can use a CPLD as well, there are still
>> 5V ones available (though more expensive than 3.3V).
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>Like the "original" Altera MAX I guess?
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>For what I think of doing I'd need about a dozen of chips. RAM, ROM, I/O and some glue as well. When I counted those, it triggered me to eventually start thinking of putting all of those into one chip, presumably only with some level adapters like on the GODIL and am now trying to learn enough to make somewhat educated decision...
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>--
>SD!
>
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>


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Received on 2013-08-26 17:01:27

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