Re: FPGA/CPLD different approach

From: Mark McDougall <msmcdoug_at_iinet.net.au>
Date: Mon, 26 Aug 2013 09:47:15 -0400
Message-ID: <pwil3emlsq721jfh6es8lj18.1377524835248@email.android.com>
Generally CPLD's don't have any SRAM. FPGA's have SRAM that can be used to implement ROM or RAM. The amount depends on the size of the device, but ordinarily you'd have enough for a small boot ROM.



Sent from my ASUS Pad

silverdr@wfmh.org.pl wrote:

>
>On 2013-08-26, at 14:38, Michał Pleban wrote:
>
>>> I understand. What If I forget the CPU emulation and want to build only some RAM, ROM and one or two 8bit bi-directinal I/O ports, all available for the original CPU to interact with - what would you suggest? Can one easily make such structures (RAM, ROM, I/O port) available for 6502 from within a CPLD/FPGA and which would be "better" in such case?
>> 
>> ROM and RAM are costly in terms of re-programmable logic. If you need
>> these, you will end up using a FPGA anyway.
>
>Why is it so? I read somewhere in Altera docs that /ROM/ is not available in [their MAX series] CPLDs. Does that mean it is not available in /any/ of them? Sorry if that's a n00b question but I also read somewhere that FPGAs have to be given some external boot rom, while CPLDs don't.
>
>> If you need only I/O, then you can use a CPLD as well, there are still
>> 5V ones available (though more expensive than 3.3V).
>
>Like the "original" Altera MAX I guess?
>
>For what I think of doing I'd need about a dozen of chips. RAM, ROM, I/O and some glue as well. When I counted those, it triggered me to eventually start thinking of putting all of those into one chip, presumably only with some level adapters like on the GODIL and am now trying to learn enough to make somewhat educated decision...
>
>-- 
>SD!
>       Message was sent through the cbm-hackers mailing list
1,jja^qiɚXX
Received on 2013-08-26 17:00:04

Archive generated by hypermail 2.2.0.