Re: C64 buses when RESET is asserted

From: Gerrit Heitsch <>
Date: Mon, 08 Apr 2013 22:53:48 +0200
Message-ID: <>
On 04/08/2013 10:38 PM, wrote:
> On 2013-04-08, at 22:32, Gerrit Heitsch wrote:
>>>>> If you tristate the cpu, you still have half the cycle left for the
>>>>> write. Not much more difficult.
>>>> You also need to monitor the BA (RDY) line, otherwise you'll run into trouble when the VIC does a badline and uses the complete cycle.
>>> But - generally - if this is done on power-up, then it could possibly be done before VIC gets initialised (I assume - maybe wrong now - that it powers up with "screen disabled" state)?
>> It will still do its own read cycles even if they're dummy cycles, including the refresh cycles. You might be able to get rid of the badlines though.
> That's what I meant. Clearing the "screen disable" bit (bit 4 at SCROLY register) is the soft way to get rid of bad lines, used in many timing critical operations. If this bit is (as I expect) cleared on power-up then at least  the bad lines are not interfering and there would be no need to monitor the extra line.

Problem is, only a power down will get VIC into that state. Just a 
normal RESET will not. If it was showing a picture (which means 
badlines) before RESET, it will continue to do so after. Reason being, 
VIC doesn't have a RESET input.

So how do you make sure that the extra circuit only accesses memory 
after a power cycle (that is long enough to really reset VIC) but not 
after a user pushes the RESET button?

I think monitoring BA / RDY and taking badlines into account might be 
the easier way.


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Received on 2013-04-08 21:00:59

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