Re: ROMs replacement

From: Gerrit Heitsch <>
Date: Mon, 08 Oct 2012 17:11:11 +0200
Message-ID: <>
On 10/08/2012 03:20 AM, wrote:
> Please correct me if that's completely wrong but can't it be some sort of timing problem between the moment when all the address lines become stable and the moment _CS/_OE becomes active? I mean we have 12 address lines that are driven directly from the main board and I assume that the address bus on the main board should be already stable when appropriate _CS line is taken down by PLA. I guess the _KERNAL/_CHAROM/_BASIC /follows/ the address bus validity because those are actually the address bus values, which need to be decoded in order to trigger appropriate output, isn't it so? If this is right then we have now three lines that are not derived off address bus but are driven using actually the _CS signals themselves. This means that on one hand we have some delay in processing the _CS signal (which I don't care about now), on the other hand we propagate address bus bits at /the very same time/ as we trigger the EPROM. Might this lead to potential on-the-verge type of tim
 ing probl
ems when 12 address bits are "long" in their expected states and three only now arrive? OTOH tACC seem to be listed as identical to tCS on the EPROMs' datasheets. But maybe that's exactly the case? If they are the same then it can be easy to get off a ns or two.. ? Yeah, for the amount of time spent on this, I run out of ideas to try..

It shouldn be that kind of problem since there is still enough time for 
the data to become stable after all the lines have stabilized.

 From my checks with a scope, the _CS line for the Char-ROM is the 
slowest of them all, going LOW about 200ns after PHI0 goes LOW, so with 
a 150ns EPROM, you should still be OK and from the picture you posted, 
you still get correct looking chars so the EPROM access in general works.

Also, you said that sometimes the system comes up OK and other times it 
doesn't. To me that really looks like a floating input somewhere. Can 
you post the schematics you used? And if it works, how stable is the 
system? How long are the lines between the board and your circuit?

You can run an EPROM with _CS and _OE tied LOW and change the address 
inputs. After tAcc, you will see the the expected output on the data 
lines. That's how the PLA-replacement using a 27C512 works.


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Received on 2012-10-08 16:00:06

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