RE: CPLD/FPGA course

Yeah SSN is the responsibility of the engineer and does tend to separate
the designers from the software operators, and simply put the tools that
help manage this and other noises sources didn't exist like they do today
(but then things were a hell of a lot less dense).  In this case it was
not my design but is sounded suspicious due to the scale of the failure.
While I have seen designers get by leaning too heavily on digital
simulations and not enough on real-life analog, and I knew where this guy
tended to have issues on past designs, this shouldn't have had the net
result of the running of  an operation on pipelined video  and
catastrophic crash.
Eventually Xilinx got involved, then they got quite, then they fessed up.
My memory is that something like a vREF, or the voltage on an piece of
substrate for a quadrant of the chip would crash or something similar in
effect.

Talking years ago but when a user finds what amounts to an architectural
flaw it stick with ya.

-----Original Message-----
From: owner-cbm-hackers@musoftware.de
[mailto:owner-cbm-hackers@musoftware.de] On Behalf Of Mark McDougall
Sent: Friday, June 08, 2012 9:20 PM
To: cbm-hackers@musoftware.de
Subject: Re: CPLD/FPGA course

On 9/06/2012 5:45 AM, Bil Herd wrote:

> I have seen Xylinx parts not work at speed, as in internal noise,
> ultimately Xylinx admitted that there were problems.  This was some of
> their big expensive parts that ultimately couldn't be "loaded up and
> ran" as this wasn't not a subtle problem where you track down a
> glitch, whole sections propagated invalid states.

[pedantic]
Xilinx, not Xylinx
[/pedantic]

Wonder if it was SSN (simultaneous switching noise)? When large portions
of a device change state at the same time, it momentarily pulls a lot of
current and also produces noise that can effect other parts of the device.

It's something you need to be mindful of even in "non-faulty" devices, but
it sounds like they had more than normal problems with it!?!

I have a design that has been running on 4 different Altera devices;
Cyclone, Cyclone II, Cyclone III & Startix III. Involves a rather wide mux
and is scalable. On the Stratix III I have it running up to 64 inputs
side.
Even on the lower-end Cyclone II it handles at least 16 inputs. On Xilinx
devices it craps out after 8 inputs. And if you try more, the synthesis
runs forever!!!

Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"

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