----- Original Message ----- From: "Gerrit Heitsch" <email@example.com> Sent: Monday, May 14, 2012 3:11 PM > On 05/14/2012 08:45 PM, MikeS wrote: >> Eh? Say what? AFAIK, with /CE low the time it takes to get valid data is >> tOE, e.g. 50ns vs. 200ns in a -200 'C256 (not that it matters at 1MHz). > > No, there is also tACC, the time from address input valid to data output > valid. And that is the time printed on the EPROM and, in most cases, the > same time as tCE. You can hide tOE inside tACC, but you cannot go below > tACC. tOE is the time to get the output drivers up, but if tACC is not > over by then, you get lots of things but not valid data. > > Gerrit -------------------------- Yes, but the address will have been valid for some time by the time /CS goes low after the delays in the CPU and PAL. IMHO the issue (if any of this is indeed an issue) is that a 250ns 2364 has an address access time of 250ns but a CS access time of *only 100ns*, whereas a 250ns 27Cxxx also has a 250ns address access time but a CE access time equal to tACC, i.e. *250ns*, so it seems to me that keeping /CE low and using /OE with its 50ns delay would be preferable and on the safe side. mike Message was sent through the cbm-hackers mailing listReceived on 2012-05-14 21:00:21
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