Re: 6510 handling of $00 and $01 registers

From: Gerrit Heitsch <>
Date: Wed, 07 Dec 2011 20:40:10 +0100
Message-ID: <>
On 12/07/2011 07:44 PM, Marko Mäkelä wrote:

> I am fairly sure that R/W and the address lines will be asserted. I
> vaguely remember that the data lines are left floating. If this is true,
> then what is written would be whatever used to be on the bus (on the
> last VIC-II access), similar to what you read from $de00..$dfff on a
> stock machine. But, note that some computers are "buggy" in this
> respect. Does anyone have an explanation for this?

You mean some machines don't have a floating data bus?

> It did not occur to me back then to
> research whether you can disable memory refresh and corrupt the RAM in
> this mode.

It's really hard to disable refresh. If you look at the _RAS signal in 
the C64, it is active twice every PHI0 cycle (display enabled). Since 
every row access will cause a refresh of the selected row (whatever 
address was present on the RAM chips at that time) you not only have to 
keep VIC from doing its refresh cycles, but also make sure neither VIC 
nor CPU will read (or write) the rows you'd like to have lose data. 
Means you'll have to at least disable the display.

Also, even though the spec states that a 4164 needs to go through a full 
refresh cycle (128 rows) in 2ms (the 41464 is 256 rows in 4ms), that 
doesn't mean a DRAM can't hold data much longer. I once read an article 
that during tests it was found that most US produced DRAM really needed 
the 2ms while most DRAM from Japan didn't lose data for hundreds of ms, 
sometimes seconds without refresh. Can't find that article anymore though.

BTW: The Sinclair Spectrum for example doesn't have a real dedicated 
refresh generator for the upper 32KB. The DRAM control circuit just lets 
every memory access (_MREQ low) perform a RAS cycle on that bank and 
uses A15 to control _CAS. Seems to work OK.


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Received on 2011-12-07 20:00:09

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