Re: 6526A synchronous serial behavior?

On Sep 21, 2011, at 3:22 PM, Segher Boessenkool wrote:

>> I'm debugging some issues with the 6526A in the 1571 drive running at 2 Mhz. When we try to send a byte to the drive via the shift register, it doesn't always get received properly. This seems to vary from drive to drive. The 6526 does transmit bytes completely reliably.
> 
> What frequency signal are you trying to receive?

It's 500 Kbit/sec inbound to the 1571. Some devices receive it just fine, others don't. I'm going to try reducing the clock rate slowly and see where it becomes reliable. If it truly is synchronous with the CNT input, it should work fine once we get below the maximum supported bitrate (whatever that is).

Different waveforms work better than others. For example, skewing more towards the clock high side of the waveform seems to work more widely than a pure 50/50 square wave.

With the drive transmitting data, I see a perfect 50/50 square wave covering 2 us per cycle and we read the data perfectly reliably. The sampling device is the ZoomFloppy, an AVR running at 16 MHz.

>> I've got a 100 Mhz digital scope and have tweaked the waveform we send, just to see what works. It seems that the drive receives the data most reliably when SRQ is on an uneven duty cycle (say 30% low, 70% high). It's still never 100% reliable though.
>> 
>> How is the CIA's synch serial input implemented? I'm curious if its logic is sensitive to glitches in DATA when CNT is held low, for example.
>> 
>> Does it just sample the DATA line when SRQ goes from low to high (externally clocked)? Or does it use Phi2 as a sampling clock and all transitions have to be synchronized to Phi2? The latter seems unlikely.
> 
> I haven't seen what the 6526 chip does yet, but both the 6502 and 6522
> synchronise all asynchronous signals to phi2; that is, the internal
> signal can only change during phi2, and the (external) signal isn't
> allowed to change faster than once per two full clock periods.
> 
> That's of course not proof it is like this on the 6526, but it's perhaps
> the best assumption to make until we know more.

If that's the case, then it may just be an issue of CNT changing too quickly. By the Nyquist limit, you need to sample at 2x but that assumes perfect synchronization (clock stable, no skew). Since the drive's Phi2 is at 2 MHz, that means we could do 500 Kbit/sec if synchronized.

However, with skew, you really want to do 4x (2 samples for each low and high clock). So that would mean only 250 Kbit/sec.

>> What are the setup/hold requirements for the external CNT pin? I've read the data sheet, but the waveforms and timing diagram are more for the CPU talking to the 6526, not for external inputs.
> 
> If it says anything, I don't see it.


I'd really love to know what the shift register input logic looks like. Anyone decap a 6526 to find out? Or have a 6526 schematic? If it is just sampling CNT on every Phi2 rising edge, for example, that could explain this issue.

-Nate


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