Hi Nate, > I'm debugging some issues with the 6526A in the 1571 drive running > at 2 Mhz. When we try to send a byte to the drive via the shift > register, it doesn't always get received properly. This seems to > vary from drive to drive. The 6526 does transmit bytes completely > reliably. What frequency signal are you trying to receive? > I've got a 100 Mhz digital scope and have tweaked the waveform we > send, just to see what works. It seems that the drive receives the > data most reliably when SRQ is on an uneven duty cycle (say 30% > low, 70% high). It's still never 100% reliable though. > > How is the CIA's synch serial input implemented? I'm curious if its > logic is sensitive to glitches in DATA when CNT is held low, for > example. > > Does it just sample the DATA line when SRQ goes from low to high > (externally clocked)? Or does it use Phi2 as a sampling clock and > all transitions have to be synchronized to Phi2? The latter seems > unlikely. I haven't seen what the 6526 chip does yet, but both the 6502 and 6522 synchronise all asynchronous signals to phi2; that is, the internal signal can only change during phi2, and the (external) signal isn't allowed to change faster than once per two full clock periods. That's of course not proof it is like this on the 6526, but it's perhaps the best assumption to make until we know more. > What are the setup/hold requirements for the external CNT pin? I've > read the data sheet, but the waveforms and timing diagram are more > for the CPU talking to the 6526, not for external inputs. If it says anything, I don't see it. Segher Message was sent through the cbm-hackers mailing listReceived on 2011-09-21 23:00:02
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