I'm debugging some issues with the 6526A in the 1571 drive running at 2 Mhz. When we try to send a byte to the drive via the shift register, it doesn't always get received properly. This seems to vary from drive to drive. The 6526 does transmit bytes completely reliably. I've got a 100 Mhz digital scope and have tweaked the waveform we send, just to see what works. It seems that the drive receives the data most reliably when SRQ is on an uneven duty cycle (say 30% low, 70% high). It's still never 100% reliable though. How is the CIA's synch serial input implemented? I'm curious if its logic is sensitive to glitches in DATA when CNT is held low, for example. Does it just sample the DATA line when SRQ goes from low to high (externally clocked)? Or does it use Phi2 as a sampling clock and all transitions have to be synchronized to Phi2? The latter seems unlikely. What are the setup/hold requirements for the external CNT pin? I've read the data sheet, but the waveforms and timing diagram are more for the CPU talking to the 6526, not for external inputs. Thanks for any info, Nate Message was sent through the cbm-hackers mailing listReceived on 2011-09-21 22:00:11
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