Re: on-chip flags (was: TED badlines, how do they work?)

From: Spiro Trikaliotis <>
Date: Tue, 6 Sep 2011 14:39:21 +0200
Message-ID: <>

* On Sun, Sep 04, 2011 at 10:55:15AM +0200 Segher Boessenkool wrote:

> >For example, it's known that the TED sound timers can be locked up. In
> >short, there is a 10-bit timer for each sound generators. (...most
> >probably multiplexed; at least, the PWM output on the sndout pin, and
> >also some cycle-exact test routines do suggest that). The 10-bit freq
> >register is in fact a reload value for the timer. Reload happens when
> >the incremented value of the timer is $03ff. Upon timer reload, the
> >timer is overwritten by the reload value, an external signal
> >raised, and
> >a T-flip-flop toggled - this T flip-flop is in turn the sound (square
> >wave) output itself, and also the clock for the noise generator.
> >...Now, if someone sets the reload register to $03fe, the timer locks
> >up; for each cycle, the timer increments the value, whose result is
> >always $03ff ie. the "reload" condition/output would be always
> >true, and
> >no edges would toggle the T flip-flop anymore. This is all proven by
> >"practice", it does work (locking the timer up will cause the T
> >flip-flop to stop, by test it's possible to slow the noise generator
> >down this way which is otherwise impossible, etc.).
> >
> >Odd thing is: one'd think, the T flip-flop keeps its state
> >forever, once
> >the timer was locked up. Well, that's not the case.
> I bet that's because there is no T flip-flop, but some other (simpler)
> circuit that behaves similarly.

I assume this simpler circuit is what Donald Hanson explains in his
paper ^"A VHDL conversion tool for logic equations with embedded D
latches",, downloadable at

BTW: Donald still owns an original blueprint of the 6502. I was in
contact with him (before Visual6502 surfaced); unfortunately, his mails


Spiro R. Trikaliotis                               

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Received on 2011-09-06 13:00:08

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