Re: TED badlines, how do they work?

On 09/03/2011 02:24 PM, Segher Boessenkool wrote:
>
> I don't see how the timing with two badlines can work, unless the RAM
> can read and write the old and the new value at the same time. Or maybe
> that's interleaved, hrm... While reading the bit pattern for char N on
> a text line from memory, read the character pointer and attr for char N+1
> from the SRAM; on the next memory clock, write either the char pointer
> or the attr from memory to the RAM. That makes everything completely
> symmetric between char pointer and attr (the only difference is what
> side is written); it requires the SRAM to be run at 2MHz (the VIC-II
> runs it at 1MHz).

That would work and I imagine the designers of TED were building on the 
experience gained from VIC-II. A 2MHz capable on die RAM should be 
possible. After all, the 656x-VIC-II still needed +12V for parts of the 
chip (video output drivers?) where TED managed the same with a single 
+5V supply (and produced more colors).


>>> It seems to the right of it is the X and Y decoders; and to the right
>>> of that are various registers to do with X and Y (Y on top, X at bottom
>>> -- 9 resp. 10 bits).
>>
>> Still, VIC-II had about the same amount of logic but needed a lot of
>> space for the sprite logic. Ok, TED also has the sound generator,
>> keyboard port and chipset signal generation, but still.
>
> It's hard to tell, but the TED is only about half the size of the VIC-II
> as far as I can tell. About a third or a quarter of that real estate
> is taken by the sound and timer logic (again, hard to see for sure).

The problem is that the die on the photo is labeled '7360R1' which would 
make it a HMOS-I TED which should use smaller structures than an NMOS 
VIC-II (656x). And I forgot about the timers, that would account for 
some extra space.


> Need better pics :-)

I agree... But all the TEDs I own are still working so I'm reluctant to 
give one up unless really no one has a broken one that can be send to 
the guys at visual6502...

Too bad the chip designers at MOS weren't able to use the trick Sinclair 
implemented in the ULA for the ZX spectrum. There the display byte and 
the attribute byte were fetched in a single RAS cycle using a page mode 
access, saving bus time. Needed some tricky arrangement of the address 
bits on the DRAM to make this possible. It might have eliminated the 
badlines.

  Gerrit


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