Re: 6561 (PAL VIC-I) interlace mode bit

From: Segher Boessenkool <*segher_at_kernel.crashing.org*> Date: Fri, 26 Aug 2011 17:21:37 +0200 Message-Id: <C4ED7FF0-D77D-4737-89DB-AC464B637D0F@kernel.crashing.org> · segher_at_kernel.crashing.org

I've looked at the Y decoder on the 6561 (PAL) chip.  It decodes:

Y=1   start of vblank
Y=10    end of vblank
Y=4   start of vsync
Y=7     end of vsync
Y=311  last line of (even?) frame
Y=312 and INT and not INT  last line of (odd?) frame

so interlace mode does nothing in effect: 311 is enabled on
every frame, 312 is never enabled.

Would be fun to compare with a 6560 :-)

Segher

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