Hello! W dniu 2011-01-26 11:40, Hársfalvi Levente pisze: > Small correction... 64kbits chips, although the multiplexed address > input is 8 bits wide, still need 7-bit refresh counters (128 refresh > cycles). 8 bit refresh counters and above are needed from 41464 and > 41256 (64kx4, 256kx1 = 256kbit) and on. That could be a good explanation then. So it looks like the $21 value is presented on the address bus, then something goes wrong with DRAM control lines and this value is used bogus "refresh" operation which does not refresh, but instead destroys data in given row. Does it make any sense? Regards, Michau. Message was sent through the cbm-hackers mailing listReceived on 2011-01-26 13:00:09
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