Hello! W dniu 2011-01-24 22:04, Ruud@Baltissen.org pisze: > Just an idea: it is possible that something goes wrong during the > refresh. DRAM is read/written by first negating RAS and then CAS > (plus offering a part of the address of course). Refreshing is done > by only negating RAS. > Imagine that something goes wrong during the refresh and CAS is > activated as well for one or another weird reason? $A1 end $21 have > 7 bits in common; exactly the number of address lines of a 4116 > DRAM. Yes, I have been thinking along these lines too. However, there are also two problems with this theory: * The refresh counter, 74393, is running freely and is not synchronized to anything (reset lines are always inactive). So it is not possible that someting occured always when the counter shows $21. * There are 4164 chips, so the row address is 8 bits. Regards, Michau. Message was sent through the cbm-hackers mailing listReceived on 2011-01-26 11:00:10
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