From: Bil Herd (bherd_at_idsbusiness.com)
Date: 2008-11-07 00:20:15
As we found on the C128, a VIC is like a dump truck on the loose and it don't stop for no blinking reset line. I had to laugh a few months back when I pulled out the schematics for a c128D and saw that we conditioned the reset line a little so the VIC wouldn't go clobbering the first couple of cycles in a Z80 (before the Z starts paying attention to the AEC) Bil Herd (hopefully reset my source address to whatever I signed up with a while back) -----Original Message----- From: firstname.lastname@example.org [mailto:email@example.com] On Behalf Of Jim Brain Sent: Friday, October 31, 2008 1:10 AM To: CBM Hackers Subject: Re: C64/VIC Bus state during RESET Jim Brain wrote: > If I was to turn on a C64 or VIC and hold RESET low, do any of the ICs > hold the address or data bus? in other words, if I had a RAM on the > bus (on a card, let's say), could I use another CPU not under RESET to > read/write to it? > > Jim > Never mind for C64. As Adrian pointed out, VIC-II refreshes and data pulls still occur. I don't have a VIC-20 setup to scope. Anyone remember? Jim -- Jim Brain, Brain Innovations (X) firstname.lastname@example.org Dabbling in WWW, Embedded Systems, Old CBM computers, and Good Times! Home: http://www.jbrain.com Message was sent through the cbm-hackers mailing list -- This message has been scanned for viruses and dangerous content by IDSi's MailScanner. Message was sent through the cbm-hackers mailing list
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