Re: C64/VIC Bus state during RESET

From: Jim Brain (brain_at_jbrain.com)
Date: 2008-10-31 06:10:10

Next message: Jim Brain: "serial link high level protocol thoughts?"
Previous message: Jim Brain: "C64/VIC Bus state during RESET"
In reply to: Jim Brain: "C64/VIC Bus state during RESET"
Next in thread: Bil Herd: "RE: C64/VIC Bus state during RESET"
Reply: Bil Herd: "RE: C64/VIC Bus state during RESET"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ] [ attachment ]

Jim Brain wrote:
> If I was to turn on a C64 or VIC and hold RESET low, do any of the ICs 
> hold the address or data bus?  in other words, if I had a RAM on the 
> bus (on a card, let's say), could I use another CPU not under RESET to 
> read/write to it?
>
> Jim
>
Never mind for C64.  As Adrian pointed out, VIC-II refreshes and data 
pulls still occur.

I don't have a VIC-20 setup to scope.  Anyone remember?

Jim

-- 
Jim Brain, Brain Innovations                                      (X)
brain@jbrain.com 
Dabbling in WWW, Embedded Systems, Old CBM computers, and Good Times! 
Home: http://www.jbrain.com


       Message was sent through the cbm-hackers mailing list

Next message: Jim Brain: "serial link high level protocol thoughts?"
Previous message: Jim Brain: "C64/VIC Bus state during RESET"
In reply to: Jim Brain: "C64/VIC Bus state during RESET"
Next in thread: Bil Herd: "RE: C64/VIC Bus state during RESET"
Reply: Bil Herd: "RE: C64/VIC Bus state during RESET"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ] [ attachment ]

Archive generated by hypermail pre-2.1.8.