Need help debugging IEC timing on #FujiNet

Hello all,

For those who haven't met me, I'm Thom Cherryhomes, and one of the firmware
engineers behind FujiNet, as well as being one of the talking heads of the
project.

FujiNet is, for those who don't know, an intelligent network adapter built
around the Espressif ESP32 microcontroller, with bus adaptations currently
for Atari, Adam, Apple2, and Lynx systems, with more coming, including the
IEC implementation for Commodore systems with serial ports (yes, we want to
do an IEEE-488 version too). For IEC and 488, it provides a virtual disk,
printer, and network adapter that can be controlled via standard KERNAL
methods.

It is a completely open project, in hardware, firmware, and software, and
anyone can make them, we do not ask for any licensing fees, and I do not
make any money from the project whatsoever. (Mozzwald does make money from
selling fujinets to help cover hardware development costs).

Thanks to Jaime Johnston's help and code from the Meatloaf project, we have
been able to do the initial bring-up of the device, enough to start work on
example programs, but we are having a hell of a time ironing out the bus
timings. This is where we are asking for help.

Currently, for example, we can reasonably consistently load and save
software over our network device, however, consistent switching back and
forth between LISTEN and TALK is manifesting in bus hangs, both in the
middle of sending bits, and when handling the turn-around. This does not
account for the fact that while we can get things to sort of work on the
64, we have issues with plus/4, and I haven't been able to try VIC-20, yet.

For reference, our code is here, in GitHub:
https://github.com/FujiNetWIFI/fujinet-platformio

Specifically, the code that deals with all the IEC transactions, is here:
https://github.com/FujiNetWIFI/fujinet-platformio/tree/master/lib/bus/iec

and code for a network device that uses it, is here:
https://github.com/FujiNetWIFI/fujinet-platformio/blob/master/lib/device/iec/network.cpp

and our timing table is here:
https://github.com/FujiNetWIFI/fujinet-platformio/blob/master/include/iecdefines.h#L151

We haven't nailed down a production hardware design yet, but I can provide
a prototype schematic on request.

What are the timing differences that can cause an absolute nightmare
between a c64 and a plus4? How does the 1541 deal with them?

-Thom