Re: Building a 6502 peripheral - timing

From: silverdr_at_wfmh.org.pl
Date: Sun, 18 Mar 2018 18:41:30 +0100
Message-Id: <4569D247-95FD-4C7C-AEFA-7F60602239A9@wfmh.org.pl>
> On 2018-03-17, at 00:03, Mia Magnusson <mia@plea.se> wrote:
> 
>> Doesn't it imply race condition? I mean if I stop driving the bus on
>> the falling edge, and CPU tries to read it at that very edge? Or is
>> it somehow "guaranteed" that CPU will take the data before PHI2
>> starts to fall?
> 
> The timing sheets for the CPU should give you information on for how
> long time the data bus must still be stable after PHI2 falls. 

I understand that "mos_6500_mpu_nov_1985" says THR is minimum 10ns. Need to find way how to do it effectively.

-- 
SD! - http://e4aws.silverdr.com/
Received on 2018-03-18 19:02:57

Archive generated by hypermail 2.2.0.