Re: Building a 6502 peripheral - timing

The 6502 timing is rather forgiving.

On reads, enable your databus outputs while phi2 is high, the CPU will take 
it at the falling edge.

On writes take the addresd line while phi2 is high and take the data from 
the bus at the falling edge.

You can latch the address at the rising edge of phi2 but that prevents 
working in a bus sharing system like the c64 where the VIC has the bus 
during phi2 low. That is actually the reason the 6522 does notwork directly 
in a c64.

Also, with " take the address during phi2 high " is critical like in the 
c64, as the address line may still change at the beginning of the cycle. So 
if you have IO here that e.g. clears the interrupt when reading the 
interrupt register, that may accidentally trigger here. Or if r/w is 
asserted RAM may try to write to an unstable addresss, corrupting memory. 
IIRC a similar process is responsible for a crash in a video demo on the 
C64 when address lines (or was it r/w) change at for the RAM at unexpected 
times so RAM is corrupted.

So in general (non bus sharing) it's easy, if you  create your own 
peripheral you should keep bus sharing systems in mind where address is not 
stable when phi2 goes high.

If if all that has been said before being late to the discussion

Regards
André

Am 15. März 2018 00:27:50 schrieb silverdr@wfmh.org.pl:

> > On 2018-03-15, at 00:09, Jim Brain <brain@jbrain.com> wrote:
> >
>> > Somewhere on the net I've seen schematics of using 16550 UART's on a
>> > C64. Although the 6510 differs slightly from a 6502, it could probably
>> > be used as some kind of guide.
> > 16550 is easy (Intel bus interface)
> >
> > ~WR = !(!(R/!W) * PHI2)
> > ~RD = !(R/!W * PHI2)
>
> What (exactly) ~WR and ~RD mean? Other that "something" write/read related? 
> And what about _CS?
>
> > As to the general question, I have sigrok here with the LWLA1034, and I 
> could run a timing pull of the various signals through some steady state 
> timing period, to show the relationships, when I next test the 6509 emu.  
> But, I'd want someone to consider where to pull the signals and work with 
> me.  If I have to spend lots of cycles trying to determine where to test 
> signals, it's likely to not happen.
>
> Please bear with me, I am not sure if I make myself clear on that. The 
> general questions are something like "How a peripheral chip should react 
> timing-wise to the incoming signals[*], so that causes no 6502/6510 
> interfacing problems?". "When should it start driving databus and when to 
> stop doing it on read cycle?". "When should it latch the data bits on write 
> cycle?". "What should be the relation between _CS and R_W?" ...
>
>
> * - I take that there has to be some delay of the _CS edge due to address 
> decoding.
> --
> SD! - http://e4aws.silverdr.com/