From: Jim Brain (brain_at_jbrain.com)
Date: 2004-11-04 23:14:01
>> To get around this, I thought about enabling the OCR IRQs. When they
>> are
>> triggered, depending on which (x or y) is bigger, turn on the overflow
>> IRQ. In the overflow IRQ, set pins to high and turn off toggle on match
>> mode.
>
> Yep, or the toggle feature could be enabled in the ICR interrupt
> routine.. and then disabled by the OCR IRQ.
Alas, I tried that last night, but it appears the AVR does not like having
the toggle (or set) feature changed in mid-count. In fact, I was unable
to find a combination that would let me have control of the pins again.
The ICP idea (in combination with me running the timer at full speed, as I
had previously used the /8 prescalar), though, helped with jitter a lot.
It cancelled out the accumulation of jitter, so it runs about 2-4 cycles
now (3/8uS to 1/2uS) It also frees up an IRQ, so folks can use that for
interface projects.
I determiend the Tiny versions won't work because they do not have ICP.
The only outstanding I see now is the case where the two pots are very
close to one another. In that case, the first one to fire takes 36 cycles
to complete, and if the other one fires in the 4.5uS it takes to service
the IRQ, it "pushes" the second waveform past its proper timing. I think
I need to do two things:
Rewrite the ISR routines to be pure ASM. 36 cycles is way too long to do a
line|=bit1
control&=(unsigned char)~OC1AIE
reti
The other is to decide when two values are too close, and handle the
situation with 1 IRQ.
Jim
Message was sent through the cbm-hackers mailing list
Archive generated by hypermail pre-2.1.8.