From: Jim Brain (brain_at_jbrain.com)
Date: 2004-11-01 07:48:31
>> An AVR clocked at 8Mhz should be suitable for jitterless operation if >> I'm right... > > > It is, if that is ALL you are doing, or if you can accomplish what you > need in the 256 "wait" cycles, but that's not always possible. As an update, I decided to try this. Instead of having both sides of the interface handles by different timer IRQs, I combined them, as the transfer of 1 byte of data from the originating system is clocks by a 20uS clock, which is 160uS/byte. Thus, when I see the falling edge, I transfer a byte. The transfer and the parse of the incoming byte is taken care of before the charge cycle starts, so the jitter I was seeing went completely away. However, even with no jitter, the LSB still fluctuates. It even fluctuates when I comment out all the code except the POT emulation code (and set the POTs to 127). So, the SID must not be capable of 1LSB resolution. Makes sense, as they were just paddles, who cares about the LSB? Jim -- Jim Brain, Brain Innovations email@example.com http://www.jbrain.com Dabbling in WWW, Embedded Systems, Old CBM computers, and Good Times! Message was sent through the cbm-hackers mailing list
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