Re: C64 Kernal disassembly question

From: Marko Mäkelä (
Date: 2004-05-19 17:52:35

On Tue, May 18, 2004 at 09:00:05PM -0500, Jim Brain wrote:
> Do you have a state diagram you made to show the state machine?

It's on a piece of paper somewhere, and also in a digital image.  It should
be drawn in a vector-based language, such as Metapost or SVG.

> I checked on funet, but it doesn;t look like the IEC code additions are 
> on the site (I could be looking in the wrong place).

True, I haven't published them.  I would need a volunteer to find out what
goes wrong when sending commands to a 1541.  The C2N232 can emulate a
peripheral nicely (LOAD, SAVE, OPEN, CLOSE, GET#), but for some reason, the
1541 doesn't behave when the C2N232 acts as a controller.  I wouldn't like
to release non-working code, but on the other hand I don't have the resources
(3-channel storage oscilloscope or logic analyzer) to analyze the problem.

Would you be interested in porting the C2N232 firmware to your hardware, or
to build a C2N232 clone?  Or someone else?  Any 8 MHz Atmel AVR microcontroller
with built-in UART and two hardware interrupt inputs should do.  The tape
interface routines can be stripped out.

> I was wondering if you did a timer IRQ and a CLK IRQ for the EOI handshake
> as well, or just the initial CLK HI...

Yes, I think I'm using timer IRQs on the sender side.  On the receiving side,
I'm just polling a timer/counter register with interrupts enabled.

> I had thought about using the timer IRQ to generate the 255 uS wait for
> the EOI handshake, but it made the code quite a bit more complicated.

Not necessarily:

	;; Interrupt handler: timer/counter 0 overflow.
	;; Return to the caller of sendsdelay, with interrupts disabled.
ovf0:	out TCCR0, YH		; stop the timer
	out TIMSK, YH		; disable timer/counter 0 overflow interrupt
	ldi 16, stacke-3
	out SPL, 16		; discard the return address
	ret			; return to the caller of sendsdelay, with I=0

	;; Subroutine: wait for PARAM0 microseconds
	;; and disable interrupts.
	mov ZH, PARAM0
	com ZH
	ldi 16, 2
sendsdelay1:			; alternative entry point
	out TCCR0, 16		; start timer/counter 0 at CK/8
	out TCNT0, ZH		; set timer/counter 0 to 255-PARAM0
	out TIFR, 16		; clear timer/counter 0 overflow interrupt
	out TIMSK, 16		; enable timer/counter 0 overflow interrupt
	rjmp waitirq		; wait for interrupt

	sei			; enable interrupts
	;; idle loop
	sleep			; wait for interrupt
	rjmp .-4

You can use the above code snippet under the conditions of the GNU General
Public License, version 2.


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