From: David Wood (jbevren_at_starbase.globalpc.net)
Date: 2004-02-06 12:34:52
This really depends on what architecture youre using. The only real reason to use clock stretching is because the cpu doesn't support wait states. Most modern cpu's (even the z80) support wait states so that a slow IO device can hold the cpu captive while the requested data is presented. 65xx(x) based systems use clock stretching on the processor because they dont support wait states. The solution therefore is to stall the cpu entirely while the data is made ready. (all: correct me if I'm wrong, but the 816 doesnt do wait states?) On all other systems (ISA, z80, etc) just build up some glue so that a write to the device triggers a wait state until the end of the next (internal) 1mhz cycle. You can run the devices asynchronous that way. A marginally more complex solution is something like waht the SCPU does. Provide enough buffer space to store one write to the slower IO space. This way the first write is latched immediately and the bus is released. If a second write comes in before the end of what would be a normal waitstate, then the bus is put into a wait mode. Its unavoidable, for IO devices to have waitstates on read. :-/ -David On Fri, 6 Feb 2004 email@example.com wrote: > Hi All, > > I'm familiar with the concept of clock stretching, but struggling with the > implementation.... > > >>Background: > All the IO chips in a C64 are 1MHz rated, even mostly so for the C128. If > one was to have a faster processor (or external access from say a PC), then > any read/writes to these locations would have to be done at 1MHz still. > > >>Problem: > Obviously a read/write to the I/O area can be detected (off one of the 74139 > chips or the PLA) but if the clock cycle is not aligned with the edge of the > system clock (Phi2) then any stretching will not only get you as far as the > time remaining. For example if you are already 200ns into the Phi2 high, > then the most you can stretch the clock is the remaining 300ns. > > Is the only way to do this properly to: > 1) hold the process off for the current (incomplete) cycle > 2) do the action on the next clock cycle where you will have the whole phase > available? > > I must admit I've never properly understood what the C128 manual says about > how it was done on that machine. > > Any suggestions? > - Nick > > > - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - > Your Engineering Solutions Provider > http://www.orbeng.com.au/orbital/engineeringServices/engServices.htm > - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - > PLEASE TAKE NOTE: > > The contents of this email (including any attachments) may be > privileged and confidential. Any unauthorised use of the contents > is expressly prohibited. If you have received this email in error, > please advise us immediately (you can contact us by telephone > on +61 8 9441 2311 by reverse charge) and then permanently > delete this email together with any attachments. We appreciate > your co-operation. > > Whilst Orbital endeavours to take reasonable care to ensure > that this email and any attachments are free from viruses or other > defects, Orbital does not represent or warrant that such is explicitly > the case > > (C) 2003: Orbital Engine Company (Australia) PTY LTD and its > affiliates > > Message was sent through the cbm-hackers mailing list
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