From: Baltissen, R (Ruud) (ruud.baltissen_at_abp.nl)
Date: 2003-08-21 08:17:44
Hallo Oliver, > If a new value is written to the 65816 banking register, the > VIC memory is going to be in the same 64k memory segment like > the 65816 CPU, so it will see the same data. You mean the register that generates A16..23? Very bad idea and for several reasons: - this register is refreshed during CLK2 is (L). OK, with a 14 Mhz version this wil be somewhere in the first 35 ns. but just the idea thatbthe address is changed when the VIC accesses the SRAM worries me. - You can program the 65816 to run in one segment and fetch data from another. Do you get the picture? - What about when using one of the segments above 1 MB? Extra hardware needed. - A simple configuration for the banking register is a 74ALS573 clocked by an inverted CLK0. Just try to figure out what happens the moment the 65816 is halted for any reason....... OK, I tell you: the banking register copies the data which at that moment is on the databus. And that is _NOT_ A16..23 !!! The only solution I found was stopping the clock for the 573 and that involves again extra hardware. > > What about any comments/objections against piling all VC64's > > up in the first 64 KB segment? > > Because it will take a little bit more hardware to do it.... Nope. The hardware I described before you need anyway. So the only things needed are some registerbits to tell the system what bank to use and some to tell the system what common areas should be enabled. Remark: maybe we can do without common areas within the first 64 KB as we have more then 15 MB common area somewhere else :) > Andererseits wären Schreibzugriffe auf das C64 ram sehr langsam, > und komplexer würde das Design dadurch auch werden.... > [Otherwise writes to the C64 become very slow and the design > becomes more complex] Yep, much more complex. You mentioned it youself: implementing your own PLA. And that's why favour the onboard project. Hmmm, in case you go for the cart, just an idea: what about replacing the original 64 KB DRAM by SRAM? Just tell the cart there is SRAM on the C64 so it also can run at 'full' speed when accessing it. Per wrote: > Considering that you just listed the hardware features of the > SCPU, in what way would your project be simpler..? :) Definitively cheaper :) > - perhaps a socket for a 512K sram chip? What about supporting one 'modern' 16 MB DRAM-module? -- ___ / __|__ / / |_/ Groetjes, Ruud \ \__|_\ \___| http://Ruud.C64.org =====DISCLAIMER================================================================= De informatie in dit e-mailbericht is vertrouwelijk en uitsluitend bestemd voor de geadresseerde. Wanneer u dit bericht per abuis ontvangt, verzoeken wij u contact op te nemen met de afzender per kerende e-mail. Verder verzoeken wij u in dat geval dit e-mailbericht te vernietigen en de inhoud ervan aan niemand openbaar te maken. Wij aanvaarden geen aansprakelijkheid voor onjuiste, onvolledige dan wel ontijdige overbrenging van de inhoud van een verzonden e-mailbericht, noch voor daarbij overgebrachte virussen. The information contained in this e-mail is confidential and may be privileged. It may be read, copied and used only by the intended recipient. If you have received it in error, please contact the sender immediately by return e-mail; please delete in this case the e-mail and do not disclose its contents to any person. We don't accept liability for any errors, omissions, delays of receipt or viruses in the contents of this message which arise as a result of e-mail transmission. Message was sent through the cbm-hackers mailing list
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