Re: Building an external CPU accelerator

From: Oliver Achten (
Date: 2003-08-20 23:25:13

> >>>>> "OA" == Oliver Achten <> writes:
> OA> So perhaps a low-profile SuperCPU could look like the following:
> OA> -64K high speed SRAM for caching the C64 area.
> OA> - 128K 29F010 ROM (55ns -> no delay) for BIOS/OS.
> OA> - 1 byte write cache
> OA> - mirroring disabled for $0000 - $01ff for faster execution
> OA> - expansion connector for hardwrare additions 
> OA> - perhaps a socket for a 512K sram chip?
> Considering that you just listed the hardware features of the SCPU, in
> what way would your project be simpler..? :)

The biggest simplification lies in  the lack of defining windows for certain
memory areas for faster memory writes. The SCPU has lots of registers for
this issue, this accelerator would have a fixed window @ $0000-01ff, the most
important memory area in the system, to make it possible to integrate the
logic into a smaller CPLD. Using a fast ROM instead of enabling reads to the SLOW
Roms for copying it into the ram also simplifies the circuit.

The best solution would be that in the end, the circuit would be simple
enough that everyone can re-build it without too much hassle.

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