From: Gideon Zweijtzer (gideonz_at_dds.nl)
Date: 2002-05-02 09:59:01
|>In the C-64, the VIC generates the DRAM timing, so we are just stuck with 1 |>MB/s to main board memory and/or I/O. Even IF you would be able to get 4 | |Damn.... I keep forgetting the RAS/CAS signals are fixed timing... Static |RAMs are so much more idiot proof! On the other hand, I think that the multiplexing is done asynchronously in the C-64 (with some general 74LS muxes), so maybe, with some luck, you can read two bytes in one clock cycle, but of course only from the same column or row (I also mix these up..) Static RAMs also have their pitfalls. Some brands do not allow the address to change during a read cycle (CS and OE active) but want the CS or OE to toggle to go to the new address. It is especially nasty in designs that want to do an access in every clock cycle (need to "or" the chipselect with the clock to make 'half' cycles! Yuck) Synchronous SRAM is quite interesting, too ;) Gideon Message was sent through the cbm-hackers mailing list
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