From: Andre Fachat (a.fachat_at_gmx.de)
Date: 2002-05-01 20:50:23
Hallo!
If you want to be flexible, maybe you want to have a look at my CS/A65
machine. The CPU card has a 74LS610, which maps addresses:
The address space is split into 16 blocks with 4k each and the 74LS610
provides 16 registers with 8 bits (actually 9, but the last bit has
to be set separately and provides a write-protect bit for the page)
that replace the upper 4 address bits:
	A12-15  --> index in register file --> A12-19
So each of the 16 4k blocks can be mapped from a 1M address space
separately.
Maybe you also want to include this in your CPU...
Andre
ncoplin@orbeng.com wrote:
> 
> >What about the 6509? That is a 6502 with the difference that it has
> >4 more address lines. The output values of the 4 address bits is
> >determined by the values of register 0 and 1. register 1 is used for
> >the data load and store operations in the lda (),y and sta (),y
> >opcodes and reg. 0 otherwise. (r0/r1 maybe vice versa, but in principle
> >that is it).
> 
> This chip is indeed and interesting one. The theme could be extended to
> include a full 8-bit paging offset, allowing 16MB rather than 1MB access.
> For the setting of the register one of the illegal fatal codes could be used
> as the operand.
> 
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