ruud.baltissen_at_abp.nl
Date: 2002-04-18 08:53:42
Hallo Spiro,
> This analyzer is even mentioned in my diploma thesis.
I actually build one for mine in 1986/7 :) In fact, yesterday I digged it up
out of all the rubble I collected in years. It worked on the day I had to
show it for my thesis and the day after it stopped, mostlikely to the way
how I wired it.
The design was 40 bits but could be upgraded to 64 bits. Why 40 bits? Goal:
20 addressbits, 8 databits and many controllines of the 8088 PC. It used 5
2K*8 SRAMs of 100 ns. So 4.77 MHz was doable.
The design was clocked by an internal or external clock (like PHI2 of a
C64).
You could program what bits to use as trigger and on what slope.
Last feature: the trigger could be used to start sampling 2048 samples, stop
sampling, or to sample just another 1024 samples.
AFAIk I still have the original ML program for the C64. The program for the
PC was lost due to very first virus I ever run into :(
In fact I have thought about reviving it again two times and started to make
electronic schematics of the paper ones. I'll have a look for them.
> Does anyone know what is the (most) limitating factor when
> using the PC's parallel port? Is it the usage of I/O
> address space, or the usage of the ISA bus?
IIRC we had this discussion about a year (?) ago. (no offence)
It is the usage of I/O space. When accessing I/O, the CPU is slowed down in
such a way that you only can do about 500K I/O opereations per second.
> I could obtain a PCI card for testing, .....
I don't have a PCI LPT-card as they are much to expensive :(
But I did some projects in the past where I used some memory mapped I/O. The
only limitation you then have is the limitation of the ISA-bus. Normally 8
MHz but I used a motherbord where you could configure this speed up to 12
MHz.
___
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