Re: 65GS10

From: Marko Mäkelä (
Date: 2002-04-17 21:36:42

  • Next message: peter karlsson: "Re: Swedish CBM 3032" wrote:
    > What locations $0 and $1 are concerned; in my implementation the reads are
    > always from the local PIO registers, and the writes go to the PIO registers,
    > but also to the bus, so the rest of the system *does* write those bytes into
    > RAM. I am not sure if this is the case with the original 6510.
    The real 6510 or 8502 doesn't drive the data lines when writing to 0 or 
    1.  It does drive the address bus and the R/-W line.
    > That the timing is concerned; there are some differences. From the top of my
    > head:
    > * branches take 2 cycles untaken, 4 taken, no matter if the page boundary is
    > crossed or not.
     > * implied instructions always take 1 cycle instead of 2
     > * In read/modify/write instructions, the wrong value is not written
     > first, like what was the case on the 6502.
    These will break a lot of video interrupt stuff.  It's very common 
    practice to use the 1-byte, 2-cycle instructions and conditional 
    branches for adjusting the timing, and it's also rather common to do 
    something like inc $d019 to acknowledge a raster interrupt.
    > What programs really depend on these timings? Mostly demo's and games. As I
    > said before, we are aming at a 32 MHz CPU.
    Another goal that would be worth trying is to build a portable C64 or 
    VIC-20 (selectable at boot time) in 3V3 logic.  Who really needs more 
    processing speed for their 8-bit machines?  You can always fire up an 
    emulator if you want speed, or you can program your stuff for a bigger 
    > - The CPU is going to be equiped with 32 (?) 32 bits general purpose
    > registers.
    How many flipflops does the FPGA have again?
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