Hallo Rainer,
> I always used a design which did also SWAP with 1MB/s.
How, if I may ask?
Two accesses within the upper half of PHI2 is impossible as you cannot
control RAS and CAS of the onboard DRAMs. The lower half is
controlled/needed by the VIC.
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/ __|__
/ / |_/ Groetjes, Ruud
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\___| http://Ruud.C64.org
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