Hallo Rainer, > I always used a design which did also SWAP with 1MB/s. How, if I may ask? Two accesses within the upper half of PHI2 is impossible as you cannot control RAS and CAS of the onboard DRAMs. The lower half is controlled/needed by the VIC. ___ / __|__ / / |_/ Groetjes, Ruud \ \__|_\ \___| http://Ruud.C64.org Message was sent through the cbm-hackers mailing list
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