> I had thought to count the dot clock and produce an enable for
> each phase of the dot clock, ie produce a one dot clock pulse
> for each cycle of the dot clock and AND that with the dot clock
> or its inverse, to split phi2 16 ways
Sure, that would be enough. But how do you achieve the biphase clocking
based on dotclock? The only logic chip I know which is capable of doing
biphase clocking by default is the Mach5 family from Vantis/Lattice, all
other logic chips I know need some delayed arithmetics like the one you
described to double a clock. That will result in a phase shift of the
double speed clock (somewhere between 5 and 20ns) but I don't think we'll
run into problems when dealing with 8MHz max.
The clean way of course would be using a PLL.
Rainer
--
Rainer Buchty, LRR, Technical University of Munich
Phone: +49 89 289-28401, Fax +49 89 289-28232, Room S3240
Message was sent through the cbm-hackers mailing list
Archive generated by hypermail 2.1.1.