Re: Castle Master once again

From: Marko Mäkelä (
Date: 2001-07-26 09:32:24

[I'm cross-posting this message to the new cbm-hackers list, since I don't
know if Ruud Baltissen is subscribing to the plus/4 list.  When you follow
up, please pay attention to the address to which your message will be

On Thu, 26 Jul 2001, Almos Rajnai wrote:

>  The sign [...snip...] means I removed some unimportant code parts 
> from there.

The snippet you posted didn't specify how the IRQ sources have been
initialized.  Even if interrupts are enabled on the processor, the
interrupt sources (timer, raster line comparison, etc.) can be disabled on
the TED.  Could it be like this?

To clarify: for an IRQ to be taken, the following conditions must hold
at the same time:

- the Interrupt flag in the status register is clear
- the IRQ line is asserted (pulled down to the logic '0' level)
- the processor is executing the last cycle but one of the current
  instruction (2 cycles before the start of the internal 7-cycle
  IRQ sequence)

If the IRQ line is asserted while the Interrupt flag is set in the
processor's status register and if it restores to inactive state before
the Interrupt flag is cleared (probably by writing to a TED register; I
don't remember the C16 so well), the processor won't execute the
interrupt sequence.

BTW, note that there are only 5 instructions that can affect the Interrupt
flag: SEI, CLI, BRK, PLP and RTI.  (Also the internal IRQ and NMI
sequences set the Interrupt flag after they have pushed P on the stack. I
don't know about the RESET sequence; I only have been told by Ruud
Baltissen that it keeps R/W high while 'writing' PC and maybe P to the


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