Hallo Nick, > The concept is to force a CAS-before-RAS refresh before the RAS signal is no > longer available from the VIC/PLA. The idea is to block the RAS event from > occuring normally, have a CAS-before-RAS refresh (actually just CAS, no > RAS), then allow the normal RAS through in time for a RAS-CAS read cycle to > be performed. As the resulting RAS event which is associated with the read > is smaller, the memory I assume needs to be faster acting. In order to > complete a CAS-before-RAS the memory needs to be faster. But 70ns SIMMS > should be relatively easy to obtain. Haven't thought about the above, sounds good and can be realised. To say it in other words: Forget the RAS/CAS sequence the moment the 6510 needs to access the RAM and first perform a CBR and then perform the needed action. One remark: the moment the VIC needs to steal cycles, the original scheme must work again. IMHO this won't jeopardize the refresh. __ __ __ __ __ __ __ __ __ | | | | | | | | | | | | | | | | | DOT-clock: |__| |__| |__| |__| |__| |__| |__| |__| |__ _______________________ __ | | | CLK2: __| |_______________________| ___ ________ ___________ __ | | | | | | | CAS: __| |_______| |__| |___________| ______ _____ ________ __ | | | | | | | RAS: __| |____| |_____| |______________| <-- CBR ---><--- NA ---><------ VIC ---------> NA = Normal Action The VIC timing is a wild guess, only meant as example !!! > I've never worked with DRAMs. Then I can tell you one more thing: I have some e-format PDF's here of some fast DRAM's and all say that the minimum time for CAS to be (L) is about the half of the one for RAS. Presuming the 120 ns behave the same (only paper info at home) and regarding the fact that the above blockdiagram gives you 62.5 ns IMHO for CAS, the above could work with 120 ns DRAM's. For use in 2 MHz-mode you do indeed need 60 ns DRAM's. Groetjes, Ruud http://Ruud.C64.org - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail firstname.lastname@example.org.
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