On Wed, 16 May 2001 firstname.lastname@example.org wrote: > The inspiration was to perform a CBR and a read in the processor phase of > the clock. With a 1MHz clock, 500ns is low and 500ns is high. There is a RAS > and CAS event in each phase, I assume for 200ns each? I have no > oscilliscope, but as some boards have 300ns RAMs, the signals should be > long. I think that my oldest C64 has 350ns DRAMs. They are in a ceramic sandwhich-like case (like EPROMs but no window). I haven't made any measurements either. If this idea works, it's certainly much simpler than what John and I suggested. If you have to go for programmable logic anyway (because of other features), then I think the simplest way to detect refresh cycles would be to count 1 MHz cycles with a 63-, 64- or 65-stage counter. During the power-on phase, this counter would be synchronized with the VIC-II memory refresh, which can be detected as the pattern of 5 consecutive reads from decrementing addresses. I don't think that there are any other circumstances under which the VIC-II reads from decrementing addresses. All other address counters in the VIC-II should increment. Maybe you could use as few as 3 least significant bits from the VIC-II address bus to detect this. These detected refresh cycles could be used for fully transparent DMA e.g. for debugging purposes. The bandwidth would be 5/63*985248 Hz = 78194 Hz (PAL) or 5/65*1022727 = 78671 Hz (NTSC). Marko - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail email@example.com.
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