Hallo Per, > Agreed. On a 500 MHz CPU you'll get a maximum of about 500 instruc- > tions per interrrupt, and the the interrupt latency including context > switch is usually somewhere between 200-300 cycles, iirc. I was thinking about a 486-66. Seems we can forget the idea for the moment. But within 5 years these 500-machines will be available for pennies, I hope :) Groetjes, Ruud http://Ruud.C64.org/ - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail firstname.lastname@example.org.
Archive generated by hypermail 2.1.1.