MagerValp wrote: > > CP> At the highest interrupt level it would probably be possible, but > CP> it would seriously hurt performance. It wouldn't be very useful. > > MvB> I wonder if it *is* possible, considering things like cache loss, > MvB> busted pipelines, that kind of yadda-yadda. > > Agreed. On a 500 MHz CPU you'll get a maximum of about 500 instruc- > tions per interrrupt, and the the interrupt latency including context > switch is usually somewhere between 200-300 cycles, iirc. > Hmmm... yes, I was probably a bit too optimistic. -- Christer Palm - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail firstname.lastname@example.org.
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